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Altera_Forum
Honored Contributor
17 years agoCan't achieve minimum setp and hold time error?? :((
The scenario is that I have a (1) grey code counter connected to a (2)combinational block that goes into a (3)parallel In parallel out register from there. There are 2 inputs from the Grey counte...
Altera_Forum
Honored Contributor
17 years agoRight-click on one of the failing paths and do a List Paths. You'll see detailed information you break out on the path below. 99% of the time when there's an internal hold violation, it's because you have a gated clock(i.e. there is logic on the clock path going to the memory.) If this is the case, you want to remove that so the clock directly feeds all logic, and use synchronous logic to control when the memory is written to.