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Altera_Forum's avatar
Altera_Forum
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15 years ago

can't access JTAG chain

Some time ago we purchased the Altera MAX II Development Kit, it works properly. Now we have modelled a board in a simplified form with a JTAG interface. When we transfer data we get this error messa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You don't need SRAM or a crystal clock for JTAG access. Your schematic looks fine to me. You're saying that V_CPLD_INT = 3V3. That should be ok. But I still can't find a source for it in your schematic. I can find a source for V_CPLD_IO but not for V_CPLD_INT.

Ton