Can't Access Jtag Chain, No device was deteced

1. You should look at the Power-Up Sequence section of the Power Management chapter of the cyclone v handbook (http://www.altera.com/literature/hb/cyclone-v/cyclone5_handbook.pdf). However, I would still expect the device to appear in the JTAG chain even if this power up sequence wasn't followed.

2. Check your schematic against Figure 7-17 in the same handbook (page 7-27). Do you see activity on all the JTAG signals? Do you see good signals on TMS, TCK & TDI - full voltage swing? Anything on TDO?

3. nCE, nSTATUS and CONF_DONE should be connected as per Figure 7-17.

4. CONF_DONE will remain low until the device is configured. If nCONFIG is high, nSTATUS should also be high. Do you have a pull-up on it?

Do you have a configuration device attached to your FPGA Some more info about your design might be helpful.

Cheers,

Alex

Hi Alex:

Thanks for your reply!

1, I followed the power-up sequence to driven the device and also issue the same problem, so, i also think this sequence don't make sense with the jtag access.

2, And about the schematic of the jtag part, i designed it strict followed the Figure 7-17 in the handbook, and the when i start jtag access by clicked the software (jtag chain debugger), the jtag's signals: TMS, TDI, TDO and TCK have a full voltage, but the pulse only keep a short time and then remain high (TMS, TDI) or low (TCK, TDO).

3, The nCE, nSTATUS and nCONFIG, CONF_DONE are also designed strict followed the Figure 7-17, the CONF_DONE was always in low status and the nCONFIG was always high but the nSTATUS was not, it remained in low status. And this sense is different from your describe. All of them are pull-up by the voltage 3.3V.

4, I checked them for some days, and now i tend to doubt the power system of the device, all of them are described as follow lines:

1.1V:

VCC (core voltage)

2.5V:

VCCA_FPLL, VCC_AUX, VCC_BAT,

VCCIO7A, VCCIO8A, VREFB7AN0, VREFB8AN0,

VCCPD3A, VCCPD3B4A, VCCPD5A, VCCPD7A8A

3.3V:

VCC_PGM

VCCIO2A, VREFB2AN0, VCCIO5B, VREFB5BN0,

VCCPA1A2A, VCCPD5B

1.5V:

VCCIO3A, VCCIO3B, VCCIO4A, VCCIO5A, VREFV3AN0, VREFB3BN0, VREFB4AN0, VREFB5AN0

5, The msel signals are pull-down to the gnd, as the handbook described, jtag mode is independented of them.

Looking forward your answers!

Tks angin for your last response.

Best wishes!

Eddy.cheng

If all is as you say then I suspect that one or more of the power supply pins does not have power.

Have ALL the power pins been connected correctly in the schematic? Have they ALL been connected up on the PCB? Are you confident that your board has been assembled correctly?

The fact nSTATUS remains low is not good. If you look at any of the configuration timing diagrams, nSTATUS always follows nCONFIG - unless you specifically hold nSTATUS low. I doubt you're doing that - are you? I suspect you've just connected a pull up to it.

How is DCLK connected? If all MSEL pins are tied low you're in FPP configuration mode (regardless of whether you use it or not). So, DCLK is an input signal. It should not be left floating. Tie it high or low.

Cheers,

Alex

What type of header is the jtag header?

I know its a stupid question, but if it's an un-keyed connector, are you sure you havent just connected it the wrong way round? (I used to do it all the time)

Hi Alex:

Thanks for your work of solving my question !

And I was worked out this problem ! The problem is one of a 2.5V voltage connect to the fpga pin is wrong.

Thanks you again!

Best Wishes!

Eddy

Hi;

thanks for your reply!

now i worked out this problem and the error is one of the 2.5V voltage driven the fpga pin is wrong (the voltage get out from the power-chip is good), i driven this pin from this chip direct and then the jtag become okay.

Tks.

eddy