Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHi Alex:
Thanks for your reply! 1, I followed the power-up sequence to driven the device and also issue the same problem, so, i also think this sequence don't make sense with the jtag access. 2, And about the schematic of the jtag part, i designed it strict followed the Figure 7-17 in the handbook, and the when i start jtag access by clicked the software (jtag chain debugger), the jtag's signals: TMS, TDI, TDO and TCK have a full voltage, but the pulse only keep a short time and then remain high (TMS, TDI) or low (TCK, TDO). 3, The nCE, nSTATUS and nCONFIG, CONF_DONE are also designed strict followed the Figure 7-17, the CONF_DONE was always in low status and the nCONFIG was always high but the nSTATUS was not, it remained in low status. And this sense is different from your describe. All of them are pull-up by the voltage 3.3V. 4, I checked them for some days, and now i tend to doubt the power system of the device, all of them are described as follow lines: 1.1V: VCC (core voltage) 2.5V: VCCA_FPLL, VCC_AUX, VCC_BAT, VCCIO7A, VCCIO8A, VREFB7AN0, VREFB8AN0, VCCPD3A, VCCPD3B4A, VCCPD5A, VCCPD7A8A 3.3V: VCC_PGM VCCIO2A, VREFB2AN0, VCCIO5B, VREFB5BN0, VCCPA1A2A, VCCPD5B 1.5V: VCCIO3A, VCCIO3B, VCCIO4A, VCCIO5A, VREFV3AN0, VREFB3BN0, VREFB4AN0, VREFB5AN0 5, The msel signals are pull-down to the gnd, as the handbook described, jtag mode is independented of them. Looking forward your answers! Tks angin for your last response. Best wishes! Eddy.cheng