Forum Discussion
Altera_Forum
Honored Contributor
11 years ago1. You should look at the Power-Up Sequence section of the Power Management chapter of the cyclone v handbook (http://www.altera.com/literature/hb/cyclone-v/cyclone5_handbook.pdf). However, I would still expect the device to appear in the JTAG chain even if this power up sequence wasn't followed.
2. Check your schematic against Figure 7-17 in the same handbook (page 7-27). Do you see activity on all the JTAG signals? Do you see good signals on TMS, TCK & TDI - full voltage swing? Anything on TDO? 3. nCE, nSTATUS and CONF_DONE should be connected as per Figure 7-17. 4. CONF_DONE will remain low until the device is configured. If nCONFIG is high, nSTATUS should also be high. Do you have a pull-up on it? Do you have a configuration device attached to your FPGA Some more info about your design might be helpful. Cheers, Alex