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DAndr6's avatar
DAndr6
Icon for New Contributor rankNew Contributor
7 years ago

Cannot configure stratix 10 device with provided bitstreams

The Board Test System (BTS) is able to detect the Stratix 10 FPGA. When we set the the load selector switch (SW3.3) to ON and connect the board to the internet, the factory default design seems to ...
Nooraini_Y_Intel's avatar
Nooraini_Y_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi DAndr6,

Thanks for the screen shot. Did you or Miaoqing Huang change the USB Blaster II TCK first to 16Mhz? Are you using the same Quartus version which is v17.1 since nedd to match with BTS v17.1 version? Before power up the dev kit, try to do this:

a) Disable the MAX V from the JTAG chain. Set the SW6.2 to ON to bypass the MAX V in the JTAG chain.

b) Then set the MSEL pins to JTAG mode only. You can set the MSEL pin at SW1 to 11.

Power up the board and set the USB Blaster II TCK to 16MHz or 6Mhz. Then perform auto-detect to make sure only Stratix 10 device is in the JTAG chain. Then try to program the bts_config.sof file.

Regards,

Nooraini