Can VREF be other than VCCIO/2?

@dane: The expectable real output behaviour can be reviewed from the Cyclone III Ibis files. You'll notice, that the output I/V characteristic is identical e.g. between CMOS12 and HSTL12 with same current strength.

You can get some ideas about structure of multi-I/O-standard form Altera patent US 7855577 " Using a single buffer for multiple I/O standards".

Of course, I'm partly guessing about undocumented features. But some conclusions are quite obvious, I think.