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VREF is meaningless for transmission (outputs), it only affects inputs. The acceptable input voltage range of the voltage referenced I/O standards is basically the same as for differential standards, because they are using the same differential input buffer of Altera FPGAs. If you refer to LVDS common mode specification, you'll notice, that it's considerably larger than the SSTL or HSTL VREF range.
If you refer to output behaviour, you can simply assume, that all I/O standards (except for dedicated LVDS drivers) are using the same set of highside and lowside output transistors and thus achieve the same output I/V characteristic.
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I'm not sure I understand what you mean about input ranges; are you suggesting that the transition region is the same regardless of IO standard and that they give different input ranges on the datasheet just to make it look more "typical?"
As for output characteristics, I understand that the voltages will typically swing much closer to V,out,low,min and V,out,high,max assuming the output isn't too heavily loaded. But again, if the output drivers all exhibit the same characteristic regardless of IO standard, then why go to all the trouble to list the different in/out modes?
I have a sneaky suspicion I'm missing something obvious here..
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What about memory VREF? I am having issues using DDR memory. I've connected fpga memory banks to 2.5V power supply and their VREF pins to 1.25V using two 1K resistors as divider (yes, my bad, I've saved money and didn't place special DDR memory power supply driver). Now when I power up my board, the 2.5V is OK, but I see 2.0V on VREF pin instead of 1.25V. Maybe I don't need to power VREF pin at all?
P.S. This happens when FPGA is not configured, I didn't test it configured to use memory.
P.P.S. all other banks where memory is not connected use 3.3V. Core voltage is OK.
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FWIW, 2.5V voltage divider through two 1K resistors is only 1.25mA bias current. I don't recall what kind of input currents are necessary, but you may not be giving yourself enough margin. You want the "wasteful" current through your divider network to be at least a magnitude greater than what you're using out the midpoint node of the divider network (the Vout point) so that fluctuations in the current used have a 10% or less effect on the voltage drop through the upper side resistor. You'll of course also want to make sure you have some holdup and/or decoupling caps on the output of your divider as well.
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When the FPGA isn't configured, the VREF pins are disabled with a weak pull-up, as any other I/O pin. That's why you are measuring a value different than expected. Do a new measurement with the FPGA properly configured.
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I wouldn't think it would be changing the midpoint by 60% though if the voltage divider was properly biased?
Socrates- just a sanity check- are you sure you have two 1K resistors and not accidentally two 10K resistors?
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Shorted outputs are the most popular reason for excessive current consumption, I would check the pinout file against the schematic in a first step. Also check all supply voltages and - if possible - determine which supply pins are sinking high current.
If it's your own PWB, also wiring and solder faults should be considered.
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+1
cheers,
..dane
Honored Contributor
