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But I'm not sure the Cyclone has enough margin on the transmission specs.
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VREF is meaningless for transmission (outputs), it only affects inputs. The acceptable input voltage range of the voltage referenced I/O standards is basically the same as for differential standards, because they are using the same differential input buffer of Altera FPGAs. If you refer to LVDS common mode specification, you'll notice, that it's considerably larger than the SSTL or HSTL VREF range.
If you refer to output behaviour, you can simply assume, that all I/O standards (except for dedicated LVDS drivers) are using the same set of highside and lowside output transistors and thus achieve the same output I/V characteristic.
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