allen18Occasional Contributor2 years agoSolvedCan the EMIF IP core remaining IO be used ? Hi : I have instantiated a 16-bit hard DDR4 controller in my project. It will occupy 2 banks and 51 IO pins. The two banks have a total of 96 pins. Excluding the 51 pins occupied by the DDR4 control...Show Moreallen18 to allen182 years agoIt should not be feasible, incompatible voltage standard
allen18Occasional Contributor to allen182 years agoIt should not be feasible, incompatible voltage standard
allen18Occasional Contributor to allen182 years agoIt should not be feasible, incompatible voltage standard
Recent DiscussionsThermal Resistance for 10M16SCU324A7GIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAAgilex 3 VCCLSENSE and GNDSENSEAgilex 7 JTAG Config Fails at 1% on Board #2 (Error 18950 / CONF_DONE Low) - But Board #1 WorksEPCQL512 and Remote Update IP ARRIA 10