Can the Cyclone III IO delay be adjusted dynamically?

Sorry for the double-post, but the forum is doing really strange stuff with my threads. The previous thread I started has zero postings (not even my own!). Did a moderator delete my post but not delete the thread? Sorry if I did something wrong...

Anyways:

Is it possible to adjust the Cyclone III IOE delay at runtime, or only at bitstream generation time?

In particular, the i/o buffer megafunction (altiobuf) user guide (http://application-notes.digchip.com/038/38-21601.pdf) for StratixIII+CycloneIII says that it is possible, but all the examples use the StratixIII-specific StratixII_CONFIG_IO primitive, which doesn't work on CycloneIII (or is there some trick that makes it work?).

According to the Cyclone III datasheet the input-pin-to-register and output-register-to-pin delay lines have a range of 0ps to 1000ps or more, but I need to be able to adjust this on a per-board and per-pin basis, so the values aren't known at the time the bitstream is written. I need to be able to sweep the values while checking error rates, similar to how the PLL output phases can be adjusted in real time.