Forum Discussion
jkhoo
Occasional Contributor
Occasional ContributorCan Stratix V IO pin configure with HSTL12 class 1 work at 0.8V
Hi PSG team, My i am currently sourcing 0.8V into VCCIO for very bank in stratix V and it is working. Based on DC and Switching Characteristics for statix V devices, HSTL-12 Class 1 VCCIO is paper ...
FvM
Super Contributor
Super ContributorHi,
I wasn't talking particularly about HSTL-12 IO standard. The simple fact is that neither Stratix V nor other recent Intel FPGA support any IO standard below VCCIO 1.2 V. This suggests that no device is tested is with e.g. 0.8 V.
I wasn't talking particularly about HSTL-12 IO standard. The simple fact is that neither Stratix V nor other recent Intel FPGA support any IO standard below VCCIO 1.2 V. This suggests that no device is tested is with e.g. 0.8 V.
jkhooOccasional Contributor
Occasional ContributorHi Fvm,
Noted on your point.
Regards, JJ
