can quartus break the compilation?

Is there any relationship between this "operation finished" pulse and a signal coming from a different clock domain? Even if those clock domain crossing signals are almost static, you could face metastability issues if they decide to change at a really bad time. This can create a chain of events that put state machines in strange states. You should really put synchronization registers between the two domains, just to be on the safe side. As they are slowly changing, just two D-flip-flops in series should do the trick, and will have a minimal impact on your design. If after that you still have the same phenomenon, we can definitely rule out clock domain crossing as the cause of your problem.