can quartus break the compilation?

There is 50MHz XOSC generated onboard and feeds both cpld and fpga. another 40MHz clock is generated from outside (external sma input). it is a VME card, VME communication is driven by 50MHz clock, 40MHz stuff is driven completely separately using information from VME registers, however this information is 'almost static'. i.e. changes once every five seconds or so (in case of interest see design: http://svnweb.cern.ch/world/wsvn/fi/lhc/projects/lhcb_calibrator/branches/broken_dac_pin_newlineariser/vhdl/#path_lhc_projects_lhcb_calibrator_branches_broken_dac_pin_newlineariser_vhdl_)

I have tried to make everything fully synchronous hence no async or time compensation of async should appear. it does not hang on communication. it hangs in random state machine inside fpga and it is caused by not-catching operation finished impulse (although those are always generated in the same clock domain)