can quartus break the compilation?

i had these mysterical behavioral when i started with quartus that adding signaltap lead to a different behavioral of the design.

daixiwen is correct, it was some kind of timing problem.

to specify only the input clock and maybe indirectly other clocks via a pll does not constrain the design.

do you have a fully synchronous design ?

or do you have some logic that depends upon more than only one clock ?

i had designs where a verilog code

always @ ( posedge clk or negedge nreset)

lead to nreset as a clock signal, but only for a few registers within the same modul.