can quartus break the compilation?

well, depends what is constraints. i have constrained all the clocks in the system in belief that it is sufficient. i'm not using timingquest. still old good classic timing analyser with default required fmax=100MHz. Maximum frequencies in the design are of that order. I have in the design an interface which provides communication between cpld and fpga. the clock-enable is generated in the cpld acting as a master, transported via +-10cm long pcb track into fpga. both are using 40MHz clock (the same) so one would think of phasing problems. this is however not the case as majorily it does not hang on communication. it hangs on processing of the data itself in a statemachine because it is waiting on a signal which apparently never arrives. another issue is, that if one connects stp to the affected signals, it starts to run properly.