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Altera_Forum's avatar
Altera_Forum
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8 years ago

Can one board support an Arria 10 GX *or* an Arria 10 SX?

I've looked at the vertical migration between Arria 10GX parts and I'm wondering if there is anything stopping someone from making a board that can also support an SX part.

When I put the two pin-outs (I'm referring to the F29 package here) beside each other in Excel there are exactly two dozen pins that don't have the same description. A lot of them are gnd in the GX part and vccl_hps in the SX part.

So, if I were to address these two dozen pins with zero ohm resistors, and populate those resistors according to which part I wanted to place on the board, what other problems would I run into?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi Bgrattan,

    Do you want to use same board for both GX & SX device using socket? if yes than

    Check whether configuration/dedicated pins are in same location.(For pick and place).

    If you have soc project build on Arria 10 SX it may not work (depends on IP) so take care in IP's .

    While designing a board, bring those two dozen trace on top layer.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Thanks. It occurred to me that I should have pointed out that my analysis was for the AX027 part vs. SX027. If anyone has heard of someone designing a board that can accommodate either SX or GX parts, I'd be interested in their experience.

    Also, if anyone is interested, here are the pins that are different:

    AX027

    SX027

    PIN

    GND

    VCCIO_HPS

    H13

    GND

    VCCIOREF_HPS

    J13

    GND

    VCCL_HPS

    K14

    GND

    VCCL_HPS

    L13

    GND

    VCCL_HPS

    L14

    GND

    VCCL_HPS

    M13

    GND

    VCCPLL_HPS

    J14

    NC

    GPIO2_IO0,NAND_ADQ0,SDMMC_DATA0,QSPI_CLK

    F12

    NC

    GPIO2_IO1,NAND_ADQ1,SDMMC_CMD,QSPI_IO0

    G16

    NC

    GPIO2_IO10,NAND_ADQ4,UART1_CTS_N,SDMMC_DATA6,SPIM0_SS0_N,EMAC2_MDIO,I2C_EMAC2_SDA

    E12

    NC

    GPIO2_IO11,NAND_ADQ5,UART1_RX,SDMMC_DATA7,SPIS0_CLK,EMAC2_MDC,I2C_EMAC2_SCL

    G15

    NC

    GPIO2_IO12,NAND_ADQ6,UART1_TX,QSPI_SS2,SPIS0_MOSI,EMAC0_MDIO,I2C_EMAC0_SDA

    K15

    NC

    GPIO2_IO13,NAND_ADQ7,UART1_RX,QSPI_SS3,SPIS0_SS0_N,EMAC0_MDC,I2C_EMAC0_SCL

    F13

    NC

    GPIO2_IO2,NAND_WE_N,SDMMC_CCLK,QSPI_SS0,BOOTSEL2

    D12

    NC

    GPIO2_IO3,NAND_RE_N,SDMMC_DATA1,QSPI_IO1

    J12

    NC

    GPIO2_IO4,NAND_ADQ2,SDMMC_DATA2,QSPI_IO2_WPN

    H12

    NC

    GPIO2_IO5,NAND_ADQ3,SDMMC_DATA3,QSPI_IO3_HOLD

    F14

    NC

    GPIO2_IO6,NAND_CLE,SDMMC_PWR_ENA,SPIM0_SS1_N,SPIS0_MISO,BOOTSEL1

    G13

    NC

    GPIO2_IO7,NAND_ALE,QSPI_SS1,SPIM0_CLK,BOOTSEL0

    J15

    NC

    GPIO2_IO8,NAND_RB,UART1_TX,SDMMC_DATA4,SPIM0_MOSI,EMAC1_MDIO,I2C_EMAC1_SDA

    H15

    NC

    GPIO2_IO9,NAND_CE_N,UART1_RTS_N,SDMMC_DATA5,SPIM0_MISO,EMAC1_MDC,I2C_EMAC1_SCL

    F16

    NC

    HPS_CLK1

    G14

    NC

    HPS_nPOR

    K11

    NC

    HPS_nRST

    K12

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hello, you may have to consider the fact if you are using SX device, the HPS EMIF I/O is located on the FPGA I/O bank. Hence, it is not just the matter of the power pins and the HPS Dedicated I/Os (there are HPS 17 dedicated I/Os in Arria 10). You will need to make sure that the board reserves the HPS EMIF I/O so that the HPS in the SX device can use them