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Altera_Forum's avatar
Altera_Forum
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8 years ago

Can not simulate MAX10 with Differential IO buffers (quartus prime)

Hello,

I instantiated a true differential output buffer and when I try to simulate I get the following: 

#  Top level modules:#      altera_gpio_lite#  End time: 08:57:10 on Jan 31,2018, Elapsed time: 0:00:00#  Errors: 0, Warnings: 0#  vlog -sv "/home/swinchen/quartus/robot_board/output_buffer_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv" -work output_buffer#  Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016#  Start time: 08:57:10 on Jan 31,2018#  vlog -reportprogress 300 -sv /home/swinchen/quartus/robot_board/output_buffer_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv -work output_buffer #  ** Fatal: Unexpected signal: 11.#  ** Error: /home/swinchen/quartus/robot_board/output_buffer_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv(38): in protected region#  End time: 08:57:10 on Jan 31,2018, Elapsed time: 0:00:00#  Errors: 2, Warnings: 0#  ** Error: /opt/intelFPGA_lite/17.1/modelsim_ase/linuxaloem/vlog failed.#  Error in macro ./robot_board_run_msim_rtl_vhdl.do line 22#  /opt/intelFPGA_lite/17.1/modelsim_ase/linuxaloem/vlog failed.#      while executing#  "vlog -sv "/home/swinchen/quartus/robot_board/output_buffer_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv" -work output_buffer"#  #  stdin: <EOF>

Does anyone know a way to fix this?

I tried to manually instantiate a fiftyfivenm_io_obuf but I could not find documentation on what the seriesterminationcontrol input was.

Thanks,

- Sam

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    What do you want to achieve? I doubt that there is much use in simulating a differential IO buffer. Hardware features like serial termination are not modelled in functional simulation.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    --- Quote Start ---

    What do you want to achieve? I doubt that there is much use in simulating a differential IO buffer. Hardware features like serial termination are not modelled in functional simulation.

    --- Quote End ---

    I am not trying to simulate the differential buffer. My test bench simulates a component inside my design. Just having the differential buffer in my top-level structural design file is enough to cause this error.