Forum Discussion
EugenyB
Occasional Contributor
Occasional ContributorCan not make PLL dynamic reconfiguration (without ALTPLL_RECONFIG)
Using Cyclone 3 and Quartus 13.1.
The result is PLL changes clock speed to wrong value (much slower that should be), scandone goes high, and PLL does not lock.
What I do:
1. In megawizard con...
I found the solution to the problem. Information is buried in ALTPLL and ALTPLL_RECONFIG documents in different places, people who do not have deep overview of the architecture would hardly match different, but related pieces of info. For cyclone 3 I must activate PLL areset pin for one reconfig clock cycle after PLL raises scandone.
Ash_R_Altera
Regular Contributor
Regular ContributorHi,
Just saw your thread. Looks like you managed to resolve the issue on your own. As you correctly pointed out, areset signal is important to be asserted and deasserted.
Regards
