Forum Discussion
Occasional ContributorCan not make PLL dynamic reconfiguration (without ALTPLL_RECONFIG)
I found the solution to the problem. Information is buried in ALTPLL and ALTPLL_RECONFIG documents in different places, people who do not have deep overview of the architecture would hardly match different, but related pieces of info. For cyclone 3 I must activate PLL areset pin for one reconfig clock cycle after PLL raises scandone.
Occasional ContributorI have made design using ALTPLL_RECONFIG and its simulation behaves the same erratic way - scandone goes high and does not get back low - with busy stuck high.
Occasional ContributorI found the solution to the problem. Information is buried in ALTPLL and ALTPLL_RECONFIG documents in different places, people who do not have deep overview of the architecture would hardly match different, but related pieces of info. For cyclone 3 I must activate PLL areset pin for one reconfig clock cycle after PLL raises scandone.
