Can not make PLL dynamic reconfiguration (without ALTPLL_RECONFIG)
Using Cyclone 3 and Quartus 13.1.
The result is PLL changes clock speed to wrong value (much slower that should be), scandone goes high, and PLL does not lock.
What I do:
1. In megawizard con...
I found the solution to the problem. Information is buried in ALTPLL and ALTPLL_RECONFIG documents in different places, people who do not have deep overview of the architecture would hardly match different, but related pieces of info. For cyclone 3 I must activate PLL areset pin for one reconfig clock cycle after PLL raises scandone.
Found the problem for wrong frequency. I was shifting bit 0 first. Manual says it must be bit 143 first. Kind of against logic, but why not.
However scandone is still always high after first reconfiguration. At the same time PLL locks, and everything else seems to be ok. Checked with scope, output frequencies are correct. Tried Modelsim (it is stupid not loading MIF files - thus used scan chain filled with 0s) - it also shows scandone going up and never getting low, however manual says that it must deactivate as soon as reconfiguration is complete.
Above shows the completion of the scan line write and reconfiguration
The above shows whole operation. I managed to load proper .HEX file into ROM in Modelsim, and as we see `scandone` goes high and does not fall back low in simulation (as well as in real system). Lock goes high in some time (not shown on the picture).
You can see that c4-c1 are loaded with zero counters, only c0 is being initialized.
Above picture: putting same "valid" settings to all the PLL channels does not make difference - scandone still does not return low.
Unfortunately the list of registers above does not have any enable/disable bits for specific PLL outputs (like we have checkmarks in megawizard). May loading zeroes into the counter prevent scandone to complete?
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