Can Max10 devices be filled 100% for logic utilization?

You could probably come up with a design that is 100% utilized, but I would NEVER DO THAT. It basically gives you ZERO flexibility going forward. Even your 96% utilization is something I would never do, especially in a shippable product. Is your FPGA expected to be field upgradeable, or do you plan to offer new features in the future? What happens if you find a bug that needs to be fixed, and it causes your utilization to go from 96% to 101% (ie, it does not fit). Even at 90% utilization routing may not be possible and be able to meet timing constraints.

As general practice I would not recommend utilization above the 75% (typical) to 85% (maximum) range for a shipping product. If it is just a lab or hobby project then do whatever fits.