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Altera_Forum
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Honored ContributorCan I use Stratix V to realizing 28GHz asynchorous sample
One asynchorous control signal send to Stratix V ,the jitter must be less than 0.1ns.so the sample frequence must to be at lest 20GHz .what should i do?
one way I think , can I use high speed serdes in Stratix V ? I need the cdr free running,do not lock to the input signal.and then use the clock from cdr to sample this control signal. Is this a good method? another way is using multi phase sample. Using 16 clock at 1.25Ghz,and has 1/16 phase differency one by one.and later combine this 16 ch data .Is this possible?2 Replies
Altera_ForumUsing the SERDES is probably not a good solution.
What exactly are you trying to sample? If you want to detect whether a pulse has occurred or not, you might want to consider using a high-speed flip-flop, eg., Hittite microwave has parts. Perhaps you could describe your application in more detail. Cheers, Dave- Altera_Forum
How do u ensure that that control signal is stable external of the FPGA?!
