can i use quick sorting in HDL(Verilog or VHDL)?

You are writing your verilog code thinking like a sequential C programmer. This code is NOT going to work the way you expect it to:

always @ (posedge clk) begin
if(rst) begin
	stack_num <= 0;
	set_end <= 0;
	first <= 0;
	last <= SIZE-1;
	stack[stack_num] <= last;
	stack_num <= stack_num + 1'b1;
	stack[stack_num] <= first;
	stack_num <= stack_num + 1'b1;
	pivot <= 0;
	cnt <= 0;
	loop_check <= 1'b0;
	loop_on1 <= 1'b0;
	loop_on2 <= 1'b0;
	loop_on3 <= 1'b0;
	end
else

Lines 5 thru 10 in particular are expecting to use the result of a computation in the next line (or so) and that is NOT how the non-blocking '<=' assignment works. It will evaluate the RHS based on current values, then save the result until the trigger event (enclosing posedge CLK with RST set) and then assign the result to the LHS. I can guarantee this is not what you are expecting.

You need to go and get a good verilog reference tex.t to understand blocking vs non-blocking assignment, event driven simulation, and the synthesis subset of the verilog language.

It should certainly be possible to code a quicksort module in verilog operating on a memory structure, but this is not going to work as written.