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Altera_Forum
Honored Contributor
16 years agoCan i use Jtag pins as I/O on MAX7128'S' device?
Hi All,
I'm currently playing with some MAX EPM7128S-LC84 chips, ( i have bunches of them to use ). Currently i'm programming them via the JTAG interface (4 pins) and can access the remaiing 60 IO pins for external use.....so far, so good. However, i'd like to be able to also use the JTAG pins as IO pins, making a total of 64 usable pins......( 8x 8bit ports ). If i assign the JTAG/IO pins within my design, will i still be able to program the device via JTAG? I'm assuming in programming mode, the JTAG pins go into a certain mode (or code-word) to tell the chip to go into program mode), and resort back to 'IO Mode' when not being programmed....i'm not sure if that's right or not???? Thanx in advance for any help, Marty.5 Replies
- Altera_Forum
Honored Contributor
I guess there's an additional programming specification for third parties who want to provide hardware programmer support.
- Altera_Forum
Honored Contributor
Thanx guys,
Yep, i figured as long as i program the chips via the 'parallel method' (not Jtag) then i should get those I/O's back..... Although the datasheet mentioned it (briefly) it doesn't seem to go into too much depth about it....of course i might have a different version datasheet? maybe the revisions cover it better? thanx again. Marty. - Altera_Forum
Honored Contributor
--- Quote Start --- No man you can't do that. --- Quote End --- How do you know? Simply uncheck the JTAG BST option in device options. - Altera_Forum
Honored Contributor
No man you can't do that. If you're using Quartus II I'm sure the compiler would hollar at you.
- Altera_Forum
Honored Contributor
--- Quote Start --- If i assign the JTAG/IO pins within my design, will i still be able to program the device via JTAG? --- Quote End --- No you need a parallel programmer, e.g. Altera APU. If I remember right, it's mentioned somewhere in the datasheet. But it's obvious from the fact, that JTAG has no high voltage signalling to override an existing pin assignment that disables JTAG pins.