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Altera_Forum's avatar
Altera_Forum
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14 years ago

Can i use a separate file to list all the files during compilation.

Hi i want to know whether it is possible to use a separate file to list all the files i am using in the design and i just want to use that particular file to direct the quartus tool to automatically take the file from the file list.

Like when we manuaaly add files in the GUI it becomes hectic if your project has some 100 files as in my case and plus my file list is ready i just dont want to manually add each file in the GUI. Maybe a .tcl can help but i have very less knowledge of using these .tcl file for full flow. The only knowledge i have in .tcl file was to generate timing reports using quartus_sta -t sample.tcl. So is there any such way to solve my problem.

Thanks.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    hi dave

    The example design was very useful Thankyou

    But is there a way we can automate the running of Quartus Projects after completion of running of another project

    What i am looking is that i have to run two projects say transmitter and a reciever overnight

    If i start running both simultaneously the quartus throw me an error "Out of memory" during fitting stage

    Is there a Tcl script so can automate the running of two projects one after the other

    So we can utilise the time effectively
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Is there a Tcl script so can automate the running of two projects one after the other

    --- Quote End ---

    Yes, you just use a loop in Tcl.

    For example, I have a board that has four FPGAs. Each one has an ID register and slight differences in functionality. When the design is compiled, I create a timestamp, and then run a loop where each is synthesized.

    Here's the basics of the code ...

    #  -----------------------------------------------------------------#  Build the design#  -----------------------------------------------------------------
    puts " - Building the design for the 4 FPGAs"
    #  Build timestamp#    Use the same timestamp for each of the four FPGAs.#    Timestamp is in UTC seconds.
    set timestamp 
    puts " - Build timestamp $timestamp (0x)"
    #  Time the build
    set start_build 
    #  Create configurations for each FPGA
    for {set fpga_num 0} {$fpga_num < 4} {incr fpga_num} {
       #  Time the per FPGA build
        set start_fpga 
       #  Create a working folder
        set dwork $qwork/data$fpga_num
        if {!} {
            puts " - Creating the FPGA#$fpga_num work folder; $dwork"
            file mkdir $dwork
        }
        cd $dwork
       #  Create a new project
        project_new -overwrite "data"
       #  Add the files
        data_files
       #  Setup the pinout and default constraints
        set device_type  0
        set tx_enable    1
        set rx_terminate 1
        data_pinout $device_type $fpga_num $tx_enable $rx_terminate
        
       #  Timing constraints
        data_timing_constraints
       #  Setup the generics
        set_parameter -name FPGA_NUM $fpga_num
        set_parameter -name TIMESTAMP $timestamp
       #  Process the design
        puts " - Processing the design for FPGA#$fpga_num"
        execute_flow -compile
        
       #  Use one of the following to save the settings
        project_close#     export_assignments
       #  Copy the RBF file
        puts " - Renaming the RBF file data$fpga_num.rbf"
        file copy -force "data.rbf" "$qwork/data$fpga_num.rbf"
        set end_fpga 
        set str ]
        puts " - FPGA$fpga_num build time: $str minutes"
    }
    set end_build 
    set str ]
    puts " - *** Total build time: $str minutes ***"
    #  Create the single DATA-FPGA configuration file
    cd $qwork
    puts " - Creating the configuration file data_basic.bin"
    exec cat data0.rbf data1.rbf data2.rbf data3.rbf > data_basic.bin
    

    You should be able to implement something like this.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Dave

    Thank you for the script

    Most of my issues are resolved,But a small issue that

    While executing the Script file

    "execute_flow -compile" command completes the Quartus II flow

    after this a window pops up

    "full compilation was successful (1206 warnings)"

    Then its waiting till i manually pushes the dialog box and after that it executes the "project_close" and takes up the next project for synthesis automatically as written in TCL file

    Can we close the dialog box showing the warnings through TCL script and continue with the next project as they can be checked from report files

    Thanks in advance
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    But a small issue that

    While executing the Script file

    "execute_flow -compile" command completes the Quartus II flow

    after this a window pops up

    "full compilation was successful (1206 warnings)"

    Then its waiting till i manually pushes the dialog box and after that it executes the "project_close" and takes up the next project for synthesis automatically as written in TCL file

    --- Quote End ---

    That is a 'new feature' then. I don't recall having to press Ok. The script was used under Quartus 10.1, or perhaps 9.0SP2, I forget which.

    Take a look at the help for the Tcl commands, perhaps there is an option to suppress the dialog box. The other option is to run the script using the command-line version of the synthesis tool.

    Let me know if you figure it out, and I'll make the change to my script too.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    Hi Dave

    Just inserting the TCL command "disable_msg_box" before execute_flow -compile had resolved the issue

    After inserting this Quartus flow didn't stop till the end of the script and all modules got synthesized

    Thanks for your help
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Just inserting the TCL command "disable_msg_box" before execute_flow -compile had resolved the issue

    After inserting this Quartus flow didn't stop till the end of the script and all modules got synthesized

    --- Quote End ---

    Excellent!

    Thanks for posting the fix, I'll add it to my script too :)

    Cheers,

    Dave