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Honored ContributorCan I use 3.3V VCCIO for LVDS receiving in stratix ii FPGA?
hello, I need to connect an ADC to the stratix ii FPGA by LVDS signals. The max signal frequency is 600MHz and the LVDS power of ADC side is 3.3V. Can I connect the VCCIO pins of the FPGA's IO bank5 and bank6 to 3.3V? The handbook says that they should be connect to 2.5V, but if I do so, the other IO pins in this two banks can not be connected to the 3.3V external chips. how can I deal with it?
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Altera_ForumThanks for reply!
Profit from your suggestion, I have changed my design.Now the IO bank 5 and 6 are used only for Lvds receiving and the signal-ended signals are all moved to other banks. And I tied the VCCIO for bank 5 and 6 to 2.5V, VREFB to GND. I wish I have done nothing wrong!- Altera_Forum
From the datasheet, it's clear that Stratix II needs 2.5V VCCIO in left and right IO banks. 2.5V IO standard can interface 3.3V on input and - by specification - only 3.3V LVTTL but but not 3.3V LVCMOS on output. Thus it depend on the input characteristics of conncted chips, if they are satisfied with 2.5V logic level. Also left and right bank LVDS inputs may possibly operate with a higher VCCIO and reduced performance. But there is no specification. It would be better to group VCCIO according to interface voltage needs. When ask, if pins in bank 5 and 6 can be used for 3.3V, why not using one bank for LVDS and the other for LVCMOS? When mixing single-ended and differential IO in a bank, a lot of pins can't be used due to placement rules.
