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Altera_Forum's avatar
Altera_Forum
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13 years ago

Can I set paths that have recovery error to false path?

In my sopc system, there are always recovery errors, which are from reset syncronizer module to ddr control module. Here is one path:

From Node: NiosII_CPU:soc0|NiosII_CPU_reset_clk_domain_synch_module:NiosII_CPU_reset_clk_domain_synch|data_out

To Node: NiosII_CPU:soc0|ddr_sdram:the_ddr_sdram|ddr_sdram_auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst|ddr_sdram_auk_ddr_datapath:ddr_io|ddr_sdram_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dq_captured_falling[1]

Launch Clock: i_clkgen|i_cpu_pll|altpll_component|pll|clk[0]

Latch Clock: ddr_clkddr_dqs[0]

The Launch Clock is 100 MHz.

The clock skew is -3.721 ns.

Apparently the From node is output of reset synchronizer, which provides global reset signals, whereas the To Node is inside a DDR controller, I can not trace it, because in the end it is the output of straxii_io, which I can not read source code.

And actually I do not know where this ddr_clkddr_dqs is from, I can not find it anywhere.

My question is: can I set this path to false path?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    You cannot use false paths as a general remedy to correct timing errors.

    That would be simply not performing static timing analysis.

    ddr_clk_ddr_dqs[0] should be coming from the DDR controller's DQS pin.

    The DDR controller should have .sdc constraints file; are you using it?

    That said, in this case, you probably don't care about the timing from the reset to the DQS: reset will be long done and gone before you get DQS strobes.

    So, a false path should solve it, for that case.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi Rbugalho,

    Thanks very much for the reply.

    I agree with you, setting false path is not a way to solve problem.

    I'm just thinking this path might have been syncronized on the DDR controller side, so I could set it to false path that the fit would work better for other paths.

    We tested the firmware which has this recovery error in a real board in the past, there was no problem. That's why I'm thinking to set it to false path.

    From the name, ddr_clk_ddr_dqs[0] should be a clock from dqs pin of ddr controller, if so, there should be prefix in front of it, for example, "NiosII_CPU:soc0|ddr_sdram:the_ddr_sdram|ddr_sdram_ auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst| ...", but in reality, there is not prefix.