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Altera_Forum
Honored Contributor
13 years agoYou cannot use false paths as a general remedy to correct timing errors.
That would be simply not performing static timing analysis. ddr_clk_ddr_dqs[0] should be coming from the DDR controller's DQS pin. The DDR controller should have .sdc constraints file; are you using it? That said, in this case, you probably don't care about the timing from the reset to the DQS: reset will be long done and gone before you get DQS strobes. So, a false path should solve it, for that case.