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Honored Contributor
Honored ContributorCan I set paths that have recovery error to false path?
In my sopc system, there are always recovery errors, which are from reset syncronizer module to ddr control module. Here is one path: From Node: NiosII_CPU:soc0|NiosII_CPU_reset_clk_domain_sync...
Altera_ForumHonored Contributor
Honored ContributorYou cannot use false paths as a general remedy to correct timing errors.
That would be simply not performing static timing analysis. ddr_clk_ddr_dqs[0] should be coming from the DDR controller's DQS pin. The DDR controller should have .sdc constraints file; are you using it? That said, in this case, you probably don't care about the timing from the reset to the DQS: reset will be long done and gone before you get DQS strobes. So, a false path should solve it, for that case.
