Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi Rbugalho,
Thanks very much for the reply. I agree with you, setting false path is not a way to solve problem. I'm just thinking this path might have been syncronized on the DDR controller side, so I could set it to false path that the fit would work better for other paths. We tested the firmware which has this recovery error in a real board in the past, there was no problem. That's why I'm thinking to set it to false path. From the name, ddr_clk_ddr_dqs[0] should be a clock from dqs pin of ddr controller, if so, there should be prefix in front of it, for example, "NiosII_CPU:soc0|ddr_sdram:the_ddr_sdram|ddr_sdram_ auk_ddr_sdram:ddr_sdram_auk_ddr_sdram_inst| ...", but in reality, there is not prefix.