Forum Discussion
FvM
Super Contributor
2 years agoHello,
there are two options,
1. use the limited info that can be read-out from remote update configuration register
2. embed version info to the FPGA image, e.g. version, git hash, app/factory flag and make it readable for Nios
Regards,
Frank
TKudoh
New Contributor
2 years agoHi, Frank.
Could you tell me more about option 1?
I created the JIC file that has two SOF pages using Quartus Convert programing files tool, and I set the option for boot from page1 (Application side).
Then, I confirmed that page 1 is loaded, or fallback to page 0 if page 1 is broken.
RU_RECONFIG_TRIGGER_CONDITIONS register is set as:
- When power on reset, the register is set to 0 (even if fallback to page 0).
- After reconfig from any (not broken)page, the register is set to 4 (reset triggered from logic array).
- After reconfig from broken page1, the register is set to 1 (CRC Error) and fallback to page 0.
All other registers are set to 0.
I can determine the current page with following method:
- Set the boot page as 0 when creating JIC file.
- If RU_RECONFIG_TRIGGER_CONDITIONS is 0, reconfig from page 1.
- If RU_RECONFIG_TRIGGER_CONDITIONS is 4, current page is 1.
- If RU_RECONFIG_TRIGGER_CONDITIONS is 1, current page is 0.
But, this method has two problems:
- It requires long boot time (but it is acceptable).
- Sometimes I want to switch to page 0 from page1 dynamically, but it is difficult.(Switching is possible, but cannot determine running with page 0, because RU_RECONFIG_TRIGGER_CONDITIONS is 4)
Regards,
Kudoh