Forum Discussion
New ContributorCan I apply REFCLK to the FPGA while powered down?
Hi
Based on PCIe specification, REFCLK usually comes from rootport CPU via pcie edge connector, users have no control on the CPU side to turn-on/turn-off the REFCLK supply, this is a common scenario, it is okay to continue apply the REFCLK to the FPGA when it is completely unpowered. Similar to the Rx pins, it can be drive while unpowered.
ContributorI've found this KDB answer for the REFCLK.
https://www.intel.com/content/www/us/en/support/programmable/articles/000084997.html
"The Arria® 10 device dedicated transceiver REFCLK pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver REFCLK pins during power-up and power-down sequencing of Arria 10 devices."
However, based on AN692 1.3.2. Transceiver Pin Guidance for Unpowered FPGA
Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 L-tile and H-tile device transceiver pins do not support ‘Hot-Socketing.’
Fully configure the transceiver block before driving or having any activity on the device transceiver pins.
In the handbook says that do not drive the transceiver and IO pins externally during the power-up and power-down time to avoid excess current.
For PCIe link, the suggestions are:
1) add analog switches to open the PCIe link.
2) another advice would be for you to disable to the PCIe ports on your host first, to ensure that you are not attempting to link train to a card that your system has decided to be fitted but not powered.
