Forum Discussion

fgfasfafgfdhagdszfea's avatar
fgfasfafgfdhagdszfea
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Can I apply REFCLK to the FPGA while powered down?

I have a situation where it is possible that the PCIe system could be powered-up while the board with the FPGA could be completely powered-down. The board with the FPGA doesn't share any of the power...
  • skbeh's avatar
    skbeh
    3 years ago

    Hi

    Based on PCIe specification, REFCLK usually comes from rootport CPU via pcie edge connector, users have no control on the CPU side to turn-on/turn-off the REFCLK supply, this is a common scenario, it is okay to continue apply the REFCLK to the FPGA when it is completely unpowered. Similar to the Rx pins, it can be drive while unpowered.


skbeh's avatar
skbeh
Icon for Contributor rankContributor
3 years ago

All fpga IOs are equipped with internal weak pull-up when they are powered-off, so when the IOs are being driven during powered-off, it will not damage.

fgfasfafgfdhagdszfea's avatar
fgfasfafgfdhagdszfea
Icon for New Contributor rankNew Contributor
3 years ago

I'm reading some more of the documentation and the Core Fabric document links to here for "Transceiver Pin Guidance for Unpowered FPGA"

https://www.intel.com/content/www/us/en/docs/programmable/683725/current/transceiver-pin-guidance-for-unpowered-fpga.html

Does this contradict what you are saying? This document seems to say you can't drive any of the pins when the FPGA is unpowered.

Sorry to keep harping on this, but I need to be completely sure the design won't be damaged, so I really want a specific document stating that this is safe. This document seems to say it is NOT safe.