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adamShiau's avatar
adamShiau
Icon for New Contributor rankNew Contributor
1 year ago
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Can Cyclone IV PIO Banks at 1.8V Safely Drive 3.3V I2C ICs in Open-Drain Mode?

Hi,

I’m using an FPGA Cyclone IV EP4CE30F23.

Some of the PIO banks are set to 1.8V, and I’m using an open-drain configuration to drive some I2C ICs that operate at 3.3V.

I’d like to know if this setup could damage the FPGA.

Also, where can I find the PIO voltage tolerance specifications?

Thank you!

AdamS

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  • FvM's avatar
    FvM
    1 year ago

    Hi,
    I'd refer to datasheet Table1–3. Recommended Operating Conditions for CycloneIVE Devices, Vi range -0.5 to 3.6 V for all VCCIO values.

    Open drain means the pin is switched between tri-stated (input mode) and output pulldown. No clamping action involved. Therefore I expect your intended operation should work.

    You'll generally take care for possible signal reflections exceeding the safe FPGA input voltage range. Because high level is only driven by I2C pull-up resistors, there's little risk of exceeding it, even with longer traces.

    Regards
    Frank

1 Reply

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    I'd refer to datasheet Table1–3. Recommended Operating Conditions for CycloneIVE Devices, Vi range -0.5 to 3.6 V for all VCCIO values.

    Open drain means the pin is switched between tri-stated (input mode) and output pulldown. No clamping action involved. Therefore I expect your intended operation should work.

    You'll generally take care for possible signal reflections exceeding the safe FPGA input voltage range. Because high level is only driven by I2C pull-up resistors, there's little risk of exceeding it, even with longer traces.

    Regards
    Frank