CAN controller from Opencores

I have been looking into using the CAN controller that is available from Opencores (the Verilog version). I do not know Verilog but am comfortable with VHDL. I want to modify the design for a Motorola interface (currently it has a Wishbone I/F or an 8051 I/F). It is also suppose to be SJA1000 "compatible".

I ran a very simple simulation to see what the design does with the basic control signals (chip select, read, write) in 8051 mode. There is a piece of code at the end of "can_top.v" that causes me concern. The code generates a chip select internally that is based on the read or write pulse going active (and qualified with the chip select from the outside world). I have included the code snippet below:

// Generating delayed wr_i and rd_i signals

always @ (posedge clk_i or posedge rst)

begin

if (rst)

begin

wr_i_q <= 1'b0;

rd_i_q <= 1'b0;

end

else

begin

wr_i_q <=#Tp wr_i;

rd_i_q <=#Tp rd_i;

end

end

assign cs = ((wr_i & (~wr_i_q)) | (rd_i & (~rd_i_q))) & cs_can_i;

assign rst = rst_i;

wr_i is the active high write from the outside world.

rd_i is the active high read from the outside world.

cs_can_i is the active high chip select from the outside world.

The issue is that if "wr_i" or "rd_i" occurs just before the clock edge, the resulting "cs" will be very narrow (confirmed with a simple simulation). This does not seem right to me. I would expect "cs" to be at least 1 clock cycle wide.

Has anyone used this core or can anyone shed light onto this? Am I misunderstanding something with this design? I am trying to figure out the design while trying to understand Verilog at the same time.

Any comments will be greatly appreciated.

Brent Zajac