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Altera_Forum's avatar
Altera_Forum
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16 years ago

CAN controller from Opencores

I have been looking into using the CAN controller that is available from Opencores (the Verilog version). I do not know Verilog but am comfortable with VHDL. I want to modify the design for a Motor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Theese statements,

--- Quote Start ---

wr_i_q <=#Tp wr_i;

rd_i_q <=#Tp rd_i;

--- Quote End ---

produce a delay of Tp simulation cycles in the assignment . it's just for simulation.

If it's necessary introduce some wait states, you can do it with a counter that sets cs more than one clock cycle.

I'm pretty sure you can do simply this;

--- Quote Start ---

assign cs = cs_can_i;

--- Quote End ---

because, i guess you don't manipulate external hardware slower than FPGA.