Can a Max 10 output tolerate be connected to 5V through a 10K resistor during power off, programming and configuration?

With 10K pullup to +5V, add a 33K pulldown to 0V. This will cap the node to ~3.8V when not driven by the FPGA output.

The additional 33K load to ground can easily be overdriven by an output (ie, 120uA).