CameraLink connectivity issues with a dev kit

Thank you gj_leeson. Could you please direct me to any documentation that has this pairing info for the full 28 bits? I have found that bits 24-26 are for the LVAL, FVAL and DVAL but what if the camera data is 12-bit output for example... which bit do I assign? I have searched online but I can't get the right thing.

OK, so for now I will just use the bit-pairing as is, and try to move on with my task. My camera is a Linescan grayscale camera outputting 1024 10-bit pixels for each line and at a line rate of 5kHz. I want to buffer a few lines (e.g. 600) and display on a standard monitor.

So, after CLRRX_BASE is assigned, I need to capture the required valid data and then use the on board SDRam to read and write and acts as a buffer before going onto a 800x600 resolution display or even a 1024x600 as I have 1024 pixels per line already.

For the first step of capturing the camera data, I thought something like the following module would do.

module LineScan_Capture  
        (
            iRST_n,                
            iCLK,            
            
            iDATA,            
            iLVAL,
            iDVAL,
            
            oDATA                
    );
    
input         iRST_n;                
input         iCLK; //clock of camera
input     iDATA;
input            iLVAL;
input            iDVAL;
output     oDATA;
reg  line_ccd_data;
always@(posedge iCLK or negedge iRST_n)
begin
    if(!iRST_n)
        line_ccd_data    <=    0;
    else if ({iLVAL,iDVAL}==2'b11)
        line_ccd_data    <=    iDATA;
    
end    
assign oDATA    = line_ccd_data;
endmodule

Is the code correct?

Now to do the buffering, I am not too sure how to do that. The demo code has used the FIFO megafunctions to read and write to the SDRAM. I'm trying to understand and modify them for my need to accumulate line data at the moment. Any advice on how to tackle that? I'll probably post a new query soon after I try a few times and fail :)