Camera to FIFO SD-RAM and then VGA display

I am trying to connect a linescan grayscale video camera to a DE2-115 board using CameraLink base mode and the CLR-HSMC receiver card. My aim is to buffer a few lines and display the info as a 2-D image on a VGA monitor. The camera outputs 1024 8-bit pixels per line and it has a line rate of 5kHz, which means a pixel rate of 5.1 MHz approximately.

I am facing two major problems with my task and I need your help desperately.

1. To capture the data after the CameraLink deserialization, I wrote the following code.

module LineScan_Capture  
        (
            iRST_n,                
            iCLK,            
            
            iDATA,            
            iLVAL,
            iDVAL,
            
            oDATA                
    );
    
input         iRST_n;                
input         iCLK; //clock of camera
input    iDATA;
input         iLVAL;
input         iDVAL;
output   oDATA;
reg  line_ccd_data;
always@(posedge iCLK or negedge iRST_n)
begin
    if(!iRST_n)
        line_ccd_data    <=    0;
    else if ({iLVAL,iDVAL}==2'b11)
        line_ccd_data    <=    iDATA;
    
end    
assign oDATA    = line_ccd_data;
endmodule

I think this code is doing the job by outputting the valid data. Now I want to make a '2-D frame' out of these data by joining up say 80 lines of data, and then send this to a dual FIFO SD-RAM to be used for VGA display. But how do I count the lines? I thought about making a counter that increments every time the LVAL goes from 0 to 1, but I don't know how to do that. I also thought about simply counting to 81920 (i.e. 1024 pixels x 80 lines) every time the {iLVAL,iDVAL} condition is satisfied but I am not sure if this is the correct way to do it. Any advice please?

2. Now to display this on a 640x480 VGA screen, there is a demo file that came with the CLR-HSMC card and which assumes we are using a 10-bit color 2-D camera . I am not putting all the code here but just section instantiations of modules Sdram_Control and VGA_Controller. (see attachment for the Sdram_control files)

Sdram_Control    u7(
//HOST Side                        
    .RESET_N(KEY),
    .CLK(sdram_ctrl_clk),
//FIFO Write Side 1
    .WR1_DATA({1'b0,green,blue}), // 16-bit width of data bus in/out SDRAM Controller
    .WR1(dval), // Write Request
    .WR1_ADDR(0),
    .WR1_MAX_ADDR(640*480/2), 
    .WR1_LENGTH(8'h50), //??
    
    .WR1_LOAD(!rst_n),
    .WR1_CLK(CLR_BASE_CLK),
//FIFO Write Side 2
    .WR2_DATA({1'b0,green,red}),
    .WR2(dval),
    .WR2_ADDR(23'h100000),
    .WR2_MAX_ADDR(23'h100000+640*480/2),
    .WR2_LENGTH(8'h50),
    
    .WR2_LOAD(!rst_n),
    .WR2_CLK(CLR_BASE_CLK),
//FIFO Read Side 1
    .RD1_DATA(Read_DATA1),
    .RD1(Read),
    .RD1_ADDR(0),
    .RD1_MAX_ADDR(640*480/2),
    .RD1_LENGTH(8'h50),
    .RD1_LOAD(!rst_n),
    .RD1_CLK(~VGA_CTRL_CLK),
                            
//FIFO Read Side 2
    .RD2_DATA(Read_DATA2),
    .
    .
//SDRAM Side
);
VGA_Controller    u1(
//Host Side
    .oRequest(Read),
    .iRed(Read_DATA2),
    .iGreen({Read_DATA1,Read_DATA2}),
    .iBlue(Read_DATA1),
//VGA Side
.
.
//Control Signal
.
.
);

I don't fully understand this code.

- What is WR1_LENGTH, and how do they choose this value of 8'h50?

- In WR1(dval) for my case, dval is the condition that will be high every time I count 80 lines in the previous code right?

- My data is 8-bit only. If I assign oDATA from the previous code to three 8-bit wires red, green and blue, can I do this on the FIFO side:

.WR1_DATA({4'b0000,green[7:4],blue[7:0]})

.WR2_DATA({4'b0000,green[3:0],red[7:0]})

and then on the VGA side

.iRed(Read_DATA2[7:0]),

.iGreen({Read_DATA1[11:8],Read_DATA2[11:8]}),

.iBlue(Read_DATA1[7:0]),

I know it is a lot to ask, but I have been stuck on this for too long and I would be extremely grateful for any help.