Forum Discussion
Occasional ContributorCalculate skew timing with Cyclone V and ksz9031
hello,
i have troubles with the ethernet bandwith and retransmissions (ack). after some diagnostic i think it is an timing issue.
the wire length from the fpga -> knz9031 is:
| mil | mm | m | delay | delay | |
| RX_DV | 1692,83 | 42,997882 | 4,30E-02 | 227,5E-12 | 228ps |
| RX_CLK | 1649,35 | 41,89349 | 4,19E-02 | 221,7E-12 | 222ps |
| RXD0 | 1684,72 | 42,791888 | 4,28E-02 | 226,4E-12 | 226ps |
| RXD1 | 1648,24 | 41,865296 | 4,19E-02 | 221,5E-12 | 222ps |
| RXD2 | 1681 | 42,6974 | 4,27E-02 | 225,9E-12 | 226ps |
| RXD3 | 1677,12 | 42,598848 | 4,26E-02 | 225,4E-12 | 225ps |
| TX_EN | 1625,87 | 41,297098 | 4,13E-02 | 218,5E-12 | 219ps |
| GTX_CLK | 1629,75 | 41,39565 | 4,14E-02 | 219,0E-12 | 219ps |
| TXD0 | 1633,94 | 41,502076 | 4,15E-02 | 219,6E-12 | 220ps |
| TXD1 | 1657,65 | 42,10431 | 4,21E-02 | 222,8E-12 | 223ps |
| TXD2 | 1657,33 | 42,096182 | 4,21E-02 | 222,7E-12 | 223ps |
| TXD3 | 1655,12 | 42,040048 | 4,20E-02 | 222,4E-12 | 222ps |
all wires are the same length, in every wire is an 22r resistor. the design is bought and not designed by us.
i found the following knowledge base entry:
https://www.intel.com/content/www/us/en/support/programmable/articles/000079123.html
=> TX_CLK to TXD/TX_CTL output data delay is specified as -0.85 to 0.15 ns
Datasheet 9031:
For the receive path (KSZ9031RNX to MAC), the KSZ9031RNX adds 1.2 ns typical delay to the RX_CLK output pin, with respect to RX_DV and RXD[3:0] output pins.
We use kernel v4 with u-boot and devicetree, after a lot of measuring and test,
i got the best result with this skew timing:
&gmac1 { status = "okay"; phy-mode = "rgmii"; /* 0 bis 900*/ rxd0-skew-ps = <420>; rxd1-skew-ps = <420>; rxd2-skew-ps = <420>; rxd3-skew-ps = <420>; rxdv-skew-ps = <420>; txd0-skew-ps = <360>; txd1-skew-ps = <360>; txd2-skew-ps = <360>; txd3-skew-ps = <360>; txen-skew-ps = <360>; /* 0 bis 1860*/ rxc-skew-ps = <1680>; txc-skew-ps = <1740>; max-frame-size = <3800>; };
But how could i calculate the skew timing?
Which timing should be the best, with mathematics
Thanks
35 Replies
NurinaRegular Contributor
Hello,
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Nurina
- Nurina
Hello,
Thank you for using Intel Communities.
Please allow some time while I investigate your case.
Thanks,
Nurina
- Nurina
Hi,
As far as I know, connecting it to an oscilloscope would be easiest. The calculation could be quite difficult.
Let me get back to you on the calculation method.
Regards,
Nurina
qwitzahi,
but it have to be possible to calculate the best timing,
or have i use really an oscilloscope for the timing?
our oscilloscope is too slow, for that speed
- Nurina
Also, may I know where are you adding these skew timing code? Is this directly applied to the KSZ9031 to adjust the skew?
- qwitza
Hello,
we change the skew time in the device tree.
i think that it is applied, because the transfer speed and the retransmission error change with.
thanks a lot
- Nurina
Hi,
I'm still waiting for a response from our internal team regarding the calculation. I'll let you know once I receive updates.
Regards,
Nurina
- Nurina
Hello,
I'm still waiting for internal team's response. I'll let you know of any updates.
Regards,
Nurina
- Nurina
Hello,
I'm still waiting for internal team's response. I'll let you know of any updates.
Regards,
Nurina
- qwitza
Hello,
k i am still waiting
- Nurina
Hello,
Are you using KSZ9031MNX or KSZ9031RNX?
- qwitza
Hello,
we are using the KSZ9031RNX.
thanks
- Nurina
Also, just to confirm- you have already adjusted the skew setting on the PHY and you have found the best result from there?
So now you want a method to calculate the best skew timing for confirmation? How did you know the adjustment gave the best result in the first place?
- qwitza
Hello,
in the first run, we just try different values and measured the data rate.
afte we ve more concerned with the topic, we found the information about calculating the delay.
and now we are not sure how we get the values.
i think with all the information from the first post, it should be possible to get the best delay settings.
but the fpga need some special settings
https://www.intel.com/content/www/us/en/support/programmable/articles/000079123.html
thanks
