C10GX programmed via MT25QU256ABA8E12-0SIT

I have a new version of a board that has been in use for a few years. The changes between this board and the previous revision is minimal and had little if anything to do with the Cyclone 10. The only changes around the FPGA is the LVDS clock for memory was changed from 50 MHZ (1.8V) to 100 MHz (3.3V). The clock connected to the Clkusr pin is still 100MHz (2.5V). The second change was the addition of an additional UART.

What we are seeing on this rev of the board is a very slow startup. The time ranges from a couple of seconds to several minutes. We finally tracked it down to the interface between the FPGA and the MT25QU256ABA8E12-0SIT. This is the same part we have been using for some time along with the MT25QU256ABA8E12-0AAT when the standard part is unavailable. The circuit for this is exactly as shown in the C10GX Handbook for a single EPCQ-L device.

At power up we immediately see nSTATUS AND nCONFIG go high. The nCSO0 signal and the DCLK do not go active for a long period of time (seconds to minutes). We have never seen anything like this. We also don't see anywhere in the Handbook that allows for access to these signals. The programming is set in Quartus to use the 100MHz Clkusr clock. From the handbook it looks as though that actual clock used is 60 MHz. When we see DCLK eventually go active we do see 60 MHz.

Does anyone have any ideas what could be causing this delay?

The design does include a NIOS Core that the previous revision did not have.