C10GX programmed via MT25QU256ABA8E12-0SIT

Aiman,

The timing looks exactly like Figure 144 in section 7.3.4.2 AS Configuration Timing of the Cyclone 10 GX Handbook except the DCLK never begins transitioning. The nCSO signal will transition every 7-10 ms presumably trying to restart the programming.

As I was probing the DLCK pin a couple of days ago I saw a burst of clocks and the FPGA started running. Previously I had a wire on the DCLK to be able to monitor it on the scope. I repeated the probing of the DCLK 20 times and every time there was a burst of clock pulses and the FPGA would program and begin running. I added a 33 pF capacitor to the DLCK line and now the FPGA programs every time.

I have no idea why putting a cap on the clock would suddenly make the circuit begin to work. I have 4 boards with virtually identical circuits between the C10 GX and the MT25Q device. This is the only one that has ever shown this behavior. The same thing happen on all 15 prototypes that we had built.

Do you have any idea why a cap would matter here?