New Contributor
Regular ContributorHello,
I am sorry for late replying you.
I need to understand your setup.
- no PFL is used.
- data pins directly connected from flash to FPGA(Cyclone 10 GX).
From Cyclone 10 GX user guide, PS/FPP (MSEL mode = 000) the flash is only connected to CPLD, not directly to FPGA. CPLD will handle the data transaction during configuration. For your setup, how this is handled?
The flash programming is successful because Quartus connected to CPLD via JTAG and CPLD directly connected to Flash.
To configure FPGA from flash, CPLD need to handle all the configuration signals. This is where your setup fail.
From previous experience, most common mistake from users is the option bits generated for FPGA is not the same with what has been set into CPLD/Flash. You can check in the .map report file after Quartus compilation to compare.
regards,
Farabi
New ContributorHello and thank you for the reply. I solved this over the past weekend by generating an uncompressed rbf file then, using a (non intel) tool I found on line (srecord-1.65.0-win64) to convert the rbf to an address offset intel hex file format. Then I used the convert programming file Intel tool to combine my Nios executable Hex files and the FPGA (now hex format) files into a single pof, that I used with my MFG FPGA image (with a PFL) to program the FLASH device attached to the FPGA. Using the intel convert programming file tool for direct sof to pof conversion creates data not suitable for a direct FPP loading apparently (by examining the raw files in a binary viewer I confirmed that). It would be nice(r) if quartus could convert sofs directly to hex for this purpose. Until then I will use the third party tool I found.
Thank you again.
Regular ContributorHello,
Thanks for the update. Good to hear you solved the problem.
May I know the external tool you used to convert the file?
We need to study this and do comparison what is wrong with current file converters, so we can fix it.
best regards,
Farabi
