Bus mux issues

Thanks for the reply guys.

There is somthing wierd going on, the RTL Netlist viewer looks ok from what I can tell.

At the risk of sounding dumb, Im not sure I fully understand you FmV mean when you say "use 3 bidir I/O symbols with the external sides connected to the busses and wire the internal sides accordingly" I thought that is how I have implemented it.

With further testing, instead of cutting off the AND gates, I bought the DIR signal out to a pin for the bottom 2 AND gates ( inst9 & inst10 ) and back in through another pin so I can measure whats going on, and it reads as expected but still doesnt work properly, its flakey, somtimes going tristate on readback, if I directly control the and AND gates seperatly by connecting the pin to ground and VCC it works as expected.

I seem to be having some sort of bus contention, I cant see how though, the same DIR line is used to feed the OE signal for the selected ram.

Now my design is really packed, and adding even 1 more pin makes the fitter not able to route the design. Is it possible that being so tight is causing it to act flakey?

Im going to do some more testing tonight by using the host to drive the RAM > HOST Select and Direction signals seperatly and see if it works as a whole. Im hoping it will, as it works when phsically tying them to ground or vcc.

Thanks

Andrew.