hey i dont think any of the ddr's support the full page mode.burst lengths of 2 / 4 are the only ones supported by the ddr.this increases to 8 in the ddr3. i think atrem_bond may have answered regarding the sdram memory by mistake.
the burst length will determing the number of consecutive read/write operations the ddr will perform to get the corresponding amount of data read/written. for e.g. with a burst length of 4 and a read operation with a data width on the dram size of 8, the dram will start performing a read operation from the starting address given to the next 4 '8'bit locations and will output 8-8-8-8 bits of data in all to the user. the column address will increment internally as long as the row doesnt reach the end. also,since it is ddr, the 4 read transactions will take a total of 2 clock cycles on the memory side. and you dont have to give 4 read transactions for the same. only 1 read transaction with a burst length of 4 has to be selected for the above operation and so forth.
take care
kk