Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Branch target address alignment

Hello,

To avoid line wrap burst from instruction cache masters, I want to align each branch target to 32 B cache line boundary. Is there any macro to achieve that?

More detailed description:

int main (void)

{

f1();

f2();

if (X)

insideIf();

else

insideElse();

fn();

}

I want that the value of each of these functions must be divisible by 32 without remainder.

When a branch target is not aligned to 32 Byte boundary, the instruction cache master issues wrap around burst. My slave component cannot handle the wrap burst. The slave property "BurstOnBurstBoundryOnly" will be respected by the instruction master? I am missing a documented proof of it.

Any links, help will be highly appreciated.

Thank you,

wcet

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You'd probably have to read and modify the gcc sources in order to get every branch target aligned.

    Or possibly compile to the .s and then insert the asm directive (IIRC .balign 32) before every code label - should be scriptable.

    Have you looked for options on the cpu cache? Although old memory technoligies supported 'critical word first' burst reads, newer ones don't. So I'd have thought there would be an option for it.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thanx DSL.

    I checked on the FPGA and the I$ issues wrap around burst to my slave device although the property "BurstOnBurstBoundary" is set. BTW, I found that GCC provides the following flags for optimization. They are related to alignment.

    http://gcc.gnu.org/onlinedocs/gcc-3.4.4/gcc/optimize-options.html

    -falign-functions

    -falign-labels

    -falign-loops

    -falign-jumps

    Did anybody use such flags for NIOS II F processor?

    Thanks.