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Altera_Forum
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12 years ago

Branch target address alignment

Hello, To avoid line wrap burst from instruction cache masters, I want to align each branch target to 32 B cache line boundary. Is there any macro to achieve that? More detailed descriptio...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thanx DSL.

I checked on the FPGA and the I$ issues wrap around burst to my slave device although the property "BurstOnBurstBoundary" is set. BTW, I found that GCC provides the following flags for optimization. They are related to alignment.

http://gcc.gnu.org/onlinedocs/gcc-3.4.4/gcc/optimize-options.html

-falign-functions

-falign-labels

-falign-loops

-falign-jumps

Did anybody use such flags for NIOS II F processor?

Thanks.