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Altera_Forum's avatar
Altera_Forum
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12 years ago

Branch target address alignment

Hello, To avoid line wrap burst from instruction cache masters, I want to align each branch target to 32 B cache line boundary. Is there any macro to achieve that? More detailed descriptio...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You'd probably have to read and modify the gcc sources in order to get every branch target aligned.

Or possibly compile to the .s and then insert the asm directive (IIRC .balign 32) before every code label - should be scriptable.

Have you looked for options on the cpu cache? Although old memory technoligies supported 'critical word first' burst reads, newer ones don't. So I'd have thought there would be an option for it.