Honored Contributor
Honored ContributorThank you very much for reply.
Excuse me for ignorance, while I more or less have an idea how it works, I still have issues integrating all my knowledge into the design, and I can not find implementation examples. Most of documents describe process, but none has HDL code. What is cycloneiii_rublock megawizard refers to? So let me explain how I see it. I do not use Qsys or Nios or whatever, there will be pure "user logic" in there. On power on FPGA will configure with image located at address 0 (factory image). If I want to reconfigure from this configuration, I should include ALTREMOTE_UPDATE megafunction into the design. If I want to configure to factory image, I do not need "add support for writing configuration parameters", when I toggle "reconfig" line when "busy" is inactive, FPGA will go to factory image automatically. However if I want to configure to another image than default, I need "add support for writing configuration parameters" to be able to write address of the image to reconfigure to. Now about driving ALTREMOTE_UPDATE. As I understood it runs as independent circuit after configuration completes, thus I just design circuits which support the operation of ALTREMOTE_UPDATE basing on some external events. Guide states that there's internal OSC to connect "clock" to, but I can not find how to do it. I have only 18 MHz external clock, I can use PLL to double/triple its speed, but I am not sure what will it change. (what does this clock affect - only speed of controller, but not speed of following reconfiguration?). Guide also says that circuit requires reset, while on power up I can source proper reset signal (from external system), after reconfiguration I hardly can do it. Next, how ALTREMOTE_UPDATE knows which storage device is out there? From the project's "device/pin options"? And the last. How do I perform operations on EPCS device contents - also through ALTREMOTE_UPDATE? Where're erase, write and read operations? I can not find them in the guide...
