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Altera_Forum
Honored Contributor
Honored ContributorBlockram: RAM model read/write
Hello,
Can someone point me out how I can read/write to the following blockram RAM model ? I can read and write to external SRAM, but I am not able to make this work using blockram. Could someone help?
ENTITY vram8k IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rden : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
wrclock : IN STD_LOGIC ;
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END vram8k;
vram8k_inst : work.vram8k PORT MAP (
data => v_data_sig,
rdaddress => v_address_r_sig(12 downto 0),
rdclock => Clk_Z80,
wraddress => v_address_w_sig(12 downto 0),
wrclock => Clk_Z80,
wren => vram_we_sig,
rden => vram_re_sig,
q => vram_q_sig
);
v_address_w_sig <= A - x"2000" when (A >= x"2000" and MReq_n = '0');
v_address_r_sig <= A - x"2000" when (A >= x"2000" and MReq_n = '0');
vram_we_sig <= Wr_n;
vram_re_sig <= Rd_n;
v_data_sig <= DO_CPU when (Wr_n = '0' and MReq_n = '0');
DI_CPU <= vram_q_sig when (Rd_n = '0' and MReq_n = '0' and A >= x"2000");
15 Replies
Altera_ForumI have checked the timing. Read operation needs 3 clock cycle. I have inserted this delay in the logic and will test for functionality.
I have also inverted the driving logic for control signals. Thanks guys for pointing that out .- Altera_Forum
I think the polarity is wrong also. Appears that you are sending an active low signal to the internal memory that needs an active high signal.
Put not(Wr_n) to wren and not(Rd_n) to rden and it should be correct polarity. - Altera_Forum
I understand that wr_n is active low, as usual with external RAM, but the internal RAM we signal, that's connected to wr_n isn't, thus I think the polarity is wrong.
- Altera_Forum--- Quote Start --- At least, these signals seem to have wrong polarity:
The other other point is, that the timing may be inappropriate for your design, but that can't be seen from the shown code. FPGA internal RAM act as synchronous RAM, you should check the timing to see if read and write operation occur at the intended moment. Also registered or non-registered read operation can be choosen. I wonder, why conditional assignment (a multiplexer) is used for the RAM input signals, but it shouldn't have any effect. --- Quote End --- Thanks for replying. The timing may be wrong... I will try to check this. However, the polarity in the said signals are ok. they are asserted LOW: vram_we_sig <= Wr_n vram_re_sig <= Rd_n Wr_n is the Z80 write enable signal. vram_we_sig is the RAM write enable signal. The multiplexers are there because it will address differente RAM/ROMS, and this is only some code to debug the block ram access.vram_we_sig <= Wr_n; vram_re_sig <= Rd_n; - Altera_Forum
At least, these signals seem to have wrong polarity:
The other other point is, that the timing may be inappropriate for your design, but that can't be seen from the shown code. FPGA internal RAM act as synchronous RAM, you should check the timing to see if read and write operation occur at the intended moment. Also registered or non-registered read operation can be choosen. I wonder, why conditional assignment (a multiplexer) is used for the RAM input signals, but it shouldn't have any effect.vram_we_sig <= Wr_n; vram_re_sig <= Rd_n;
